1. Field of the Invention
The present invention relates to a semiconductor device comprising an internal clock generating circuit for receiving an external clock and generating an internal clock, and more in particular to a semiconductor device comprising an internal clock generating circuit for generating a first internal clock (CLK1) in phase with an external clock and a second internal clock 180.degree. out of phase (shifted by one-half of a phase) from the external clock.
2. Description of the Related Art
In a system comprising a combination of a plurality of semiconductor devices, it is a common practice to synchronize the operations of the various parts with a clock. For this reason, semiconductor devices other than the one which generates and outputs an original clock include an internal clock generating circuit which receives the clock output from other semiconductor devices and generates an internal clock used for the internal parts thereof. A description herein will be made of a synchronized dynamic random access memory (SDRAM) as an example which performs signal input and output operations with external sources and an internal operation in synchronism with a clock. The present invention, however, is not limited to the SDRAM.
In recent years, a demand has increased for an improved data transfer rate of the SDRAM, and the clock frequency has greatly increased. With an increased clock frequency, however, the problem of the signal deterioration, etc. is posed. As described above, the data signal changes in accordance with the period of the clock, and the frequency of the data signal is one half that of the clock. In view of this, a DDR (double data rate) technique has been proposed, in which the data signal is set to the same frequency as the clock and is retrieved in synchronism with both the leading and trailing edges of the clock.
In the DDR technique, the ideal phase difference between the leading and trailing edges of a clock CLK is 180.degree.. The external clock actually retrieved, however, often has a phase difference other than 180.degree. between the leading and trailing edges due to the load of the signal line, etc. Also, the characteristics of the internal clock generating circuit frequently causes the internal clock to have a phase difference other than 180.degree. between the leading and trailing edges thereof. The resulting problem is that if a data signal is retrieved or the internal circuit is operated in synchronism with the leading and trailing edges of the internal clock, the time margin for normal operation cannot be satisfied.
In employing the DDR technique, one solution to the above-mentioned problem would be for the transmitting end of the signal to output a first clock CLK and a second clock /CLK 180.degree. out of phase in complementary relation with each other and for the receiving end of the signal to retrieve the signal in synchronism with the leading edges of CLK and /CLK. Another solution to the problem would be to generate a second internal clock exactly 180.degree. out of phase with the external clock CLK in the SDRAM using the delay locked loop (DLL) or the like technique from the external clock CLK.
A SDRAM could thus be fabricated incorporating one of the two types of internal clock generating circuits (clock input circuits) depending on the technique used for the system on which it is mounted. In other words, two types of SDRAM could be fabricated, one exclusively using a complementary clock, and the other for exclusively generating a 180.degree. clock internally.
Nevertheless, analogous semiconductors having two different specifications would be fabricated at a higher cost due to a lower production efficiency and an inefficient inventory control. The manufacturer which produced a system using such a device would also suffer from an increased cost due to an increased stockpile. Thus, a device is desirable which can be used for both a system using a complementary clock and a system which generates a 180.degree. phase clock internally.
Also, with the increase in frequency, the delay of the internal clock of the semiconductor device increases to a significant extent. For example, the layout of a semiconductor sometimes makes it necessary to arrange a data input circuit and a data output circuit at a distance from an internal clock generation circuit. In such a case, the internal clock supplied from the internal clock generation circuit to the data input circuit or the data output circuit is delayed, which causes a deviation of the data input or output operation. Also, some delay is unavoidable in the clock input buffer and the internal clock generation circuit. As long as the clock frequency is not high, such a delay poses no substantial problem. With the increase in clock frequency to 100 MHz or more, however, the situation is aggravated to a significant extent. In order to solve this problem, the present applicant proposes, in U.S. Copending applications Nos. 08/892,790 and 08/924,705, a method for completely synchronizing the internal clock supplied to the data input circuit and the data output circuit with an external clock using a variable delay line having the delay amount thereof changeable. These applications do not disclose a semiconductor device operating according to a DDR (double data rate) scheme which uses a complementary clock. It has been desired also in a DDR semiconductor that the data input/output operation can be performed totally in synchronism with an external clock.